Cerebras Plans Stacked DRAM for CS-6 to Address Wafer-Scale AI's Capacity Limit
Nexus first turns three wafer-scale engines into replaceable modules; CS-6 is meant to add DRAM above the processor, but capacity, packaging, and production dates remain undisclosed.
Original title: Hot Chips 2026: Cerebras lays out the future of wafer-scale AI — Nexus system architecture triples rack-scale performance, CS-6 wafer to incorporate stacked DRAM
Cerebras used Hot Chips 2026 to outline the next stages of its Nexus wafer-scale AI system. The current CS-4 packages three wafer-scale engines as replaceable compute modules, while the planned CS-6 would add 3D-stacked DRAM above a wafer-scale processor. That proposed change directly addresses the capacity constraint created by Cerebras' long reliance on on-chip SRAM. It is still a roadmap, however, not a memory product that has been sampled or entered production.
CS-4 is the first Nexus system. It contains three compute backpacks built around WSE-3 Turbo engines and separates those modules from power, cooling, and input-output infrastructure. Tom's Hardware reported 44GB of SRAM in each backpack, or 132GB across the system. The modular layout lets Cerebras upgrade compute and infrastructure on different schedules, but it does not remove the large capacity gap between SRAM and the memory pools found in full GPU racks.
Cerebras' technical blog identifies CS-5 as a 2027 target and sets inference-speed and efficiency objectives for future systems. Those figures are company plans and internal estimates, not independent benchmarks. The more consequential CS-6 proposal is to connect 3D-stacked DRAM to wafer-scale SRAM and compute logic through ultra-high-bandwidth links. Cerebras says the arrangement could keep more model parameters local and reduce external data movement when SRAM capacity is insufficient.
The public material does not disclose CS-6 DRAM capacity, stack height, interface bandwidth, memory supplier, bonding process, yield, or thermal design. It also gives no date for samples or commercial delivery. If the architecture reaches production, wafer-scale AI could move from being an unusual SRAM-centered system to becoming an incremental customer for stacked DRAM and advanced packaging. Without specifications, volume, and customer deployments, it would be premature to infer that DRAM orders or industry bit demand have already increased.
The next evidence to watch is a CS-6 sample, disclosed stack capacity and bandwidth, named memory and packaging partners, and data on thermals, yield, and customer model performance. Whether CS-5 arrives on its 2027 target will also test the modular Nexus upgrade path. For now, CS-6 is a technically relevant response to a capacity limitation, not a storage-market revenue signal.