Samsung Maps Three HBM Phases, Ending With a Processor Beneath DRAM

Samsung used Hot Chips 2026 to describe a three-stage path for moving more logic into high-bandwidth memory. Tom’s Hardware, reporting from the session, labels the stages cHBM, aHBM, and zHBM. The sequence starts with a customized logic base die, adds selected processing elements beneath the DRAM stack, and ends with a concept in which the processor sits directly below DRAM. It is a disclosure of architectural direction, not a committed production schedule.

The first stage, custom HBM or cHBM, retains the conventional DRAM stack while tailoring the logic underneath it to a particular accelerator. According to the report, using an advanced logic process can reduce the area occupied by interface circuitry and let the base die perform some functions previously handled by the host processor. Samsung’s second stage, advanced HBM or aHBM, would add selected processing elements to that base die. Memory-bound work could then be performed closer to the data, while compute-heavy operations would remain on the GPU.

The third stage makes the largest physical change. In the zHBM concept, the processor no longer sits beside HBM across an interposer; it is placed directly beneath the DRAM stack. Samsung’s presentation projected about 70% lower I/O power than HBM5. A separate modeled comparison with a four-stack HBM4E system projected roughly 2.3 times the DRAM bandwidth while reducing memory power by about 100 watts. These are Samsung projections reported from the session. No independent reproduction or customer-silicon result was presented in the report.

Thermals and manufacturing are central constraints. Tom’s Hardware reported that Samsung is targeting roughly four-high zHBM stacks, rather than the 12-high or 16-high arrangements possible with conventional HBM, specifically because of heat. The concept would also require wafer-on-wafer assembly and hybrid copper bonding, along with tighter co-design between DRAM and system-on-chip teams. Capacity, bandwidth, power, thermal density, and manufacturing yield therefore remain linked trade-offs.

Samsung did not provide a firm launch date for any of the three stages. The concrete starting point is the move to an advanced logic base die in HBM4; cHBM and aHBM are presented as nearer extensions, while zHBM is the longer-term endpoint. The next evidence to watch is customer participation, sample specifications, measured system power and thermals, hybrid-bonding yield, and explicit sampling and production windows. Until those appear, the roadmap should not be mistaken for a product that customers can order.