Everspin Demonstrates a 4GB CXL MRAM Platform, but Deployment Constraints Remain

Everspin demonstrated a working platform that attaches MRAM to a server through Compute Express Link at the SNIA Developer Conference. The point is not that MRAM has replaced DRAM or NAND. It is that persistent memory can be exposed through CXL memory semantics on a standard server path: data remains after power loss while a processor can address it as memory [1]. That creates a possible layer between volatile memory and SSDs for checkpointing, key-value caches and write buffers.

The demonstrated configuration is small and specific. A Supermicro server with an AMD EPYC 9355, an Alveo U250 FPGA and a Wolley controller used four 1GB DDR4 MRAM UDIMMs to form a contiguous 4GB address space [1][2]. Everspin says writes can be up to 100 times faster than NAND SSDs; that is a company benchmark, not a result independently verified on customer workloads [1]. EE Times reported that the platform passed MemTester and Google Stress App tests, and that Everspin positions it as a high-performance persistent cache rather than a NAND replacement [2].

For the storage industry, the change is at the interface rather than at capacity. CXL lets an external resource be accessed with memory semantics, potentially making persistent media that once depended on specialized slots or niche equipment easier to evaluate in servers. John Wood’s analysis is that applications genuinely constrained by recovery, logging or KV-cache latency could reduce waits associated with moving data between DRAM and SSDs. That only establishes a viable attachment path. It does not establish that cost, density or system throughput can change mainstream memory configurations.

The counter-evidence is concrete. Blocks & Files reported that the host link in the demonstration was PCIe Gen3 x8, although the controller IP supports CXL 3.2; a 4GB prototype is also far below the DRAM and flash pools common in data centers [3]. Everspin says the platform is ready for customer testing, not that it has announced a volume product or deployment [1]. The next tests are latency, sustained bandwidth, cost per GB and recovery behavior under real workloads, plus design wins using faster links. Until those data arrive, this is a testable architecture demonstration, not evidence that MRAM demand or NAND share has already changed.