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Samsung Claims 3.01× LPDDR5X-PIM Inference Throughput, but the Output Mismatch Remains Unresolved

A Llama 3.1 8B test shows less data movement and higher throughput, but the outputs differed and comparable accuracy and system power remain unproven.

John Wood
Diagram comparing repeated processor-memory transfers in traditional LPDDR5X with selected operations executed near memory in LPDDR5X-PIM
MemoryTicker original diagram. Samsung's Llama 3.1 8B test claimed 3.01× token throughput, 2.28× runtime and 8× internal bandwidth; the reported outputs differed and accuracy optimization was ongoing. · Image: MemoryTicker

Samsung presented LPDDR5X-PIM at Hot Chips 2026, adding basic processing logic to low-power memory. Tom’s Hardware and ServeTheHome, reporting from the presentation materials, said Samsung ran Llama 3.1 8B on an unidentified edge AI accelerator. Runtime fell from 12.3 seconds to 5.4 seconds, a 2.28× gain; output rose from 27.0 to 81.3 tokens per second, a 3.01× gain; and internal bandwidth increased from 76.8GB/s to 614GB/s, or about eightfold. These are preliminary Samsung benchmark claims and have not been independently reproduced.

The problem PIM targets is data movement rather than capacity. In a conventional inference system, the processor repeatedly fetches model weights and intermediate results from memory. When bandwidth becomes the bottleneck, compute units wait for data and the transfers themselves consume energy. Moving suitable parallel operations closer to memory can shorten that path. This does not mean an entire model runs inside memory; it means selected work no longer has to make every round trip to the host processor.

The notable change is that PIM is moving beyond high-bandwidth-memory and server experiments into the LPDDR class. LPDDR serves systems with tighter power and space limits. If the gain survives real workloads, personal AI devices, edge servers, and other local-inference systems could benefit. The official Hot Chips program lists it as an LPDDR-based PIM solution for AI inference, confirming a formal technical disclosure but not the performance figures.

The most important counter-evidence is the output itself. Tom’s Hardware reported that the PIM and conventional LPDDR5X runs produced different outputs. An attendee challenged this at the session; Samsung said accuracy optimization is ongoing and that it expects the performance benefit to remain. Until output quality is comparable, 3.01× describes throughput in this test—not usable inference performance. Public reporting also does not identify the accelerator or batch size. Samsung said overall power should not rise while acknowledging that peak power would be “much higher,” but no comparable system-level measurement was disclosed.

The defensible conclusion today is that Samsung has shown a plausible way to reduce data movement, not that 3.01× throughput will persist at equal accuracy, controlled power, and in a production software stack. The first evidence to watch is a repeat test with matching output or a standard accuracy metric, followed by complete system-power data, developer tooling and supported operators, customer sampling, and firm cost and production timing. Only then can demonstration speed become deployable product value.