Micron leaves 4F² DRAM off its roadmap, shifting the density debate to extended 6F² and 3D designs

Micron said during its October 21 technology webinar that 4F² DRAM is not on its product roadmap at present. Tom’s Hardware and TrendForce separately reported Scott DeBoer, Micron’s president and chief technology and products officer, as saying that DRAM density is set principally by capacitor pitch and dimensions, not simply by changing the nominal transistor layout from 6F² to 4F². Those are Micron’s technical and economic claims; they do not independently establish competitors’ yields, costs or product plans.

The choice matters because 4F² is commonly described as a route to a cell footprint about one-third smaller than 6F², making it a candidate for extending planar DRAM scaling. But a smaller layout label is not the same as saleable bit density. The capacitor still occupies the structure above the transistor. If capacitor pitch does not shrink with the underlying layout, the change below it need not translate proportionally into more usable bits per wafer. Micron says 4F² adds process complexity and cost and eventually encounters physical scaling limits. Public material does not provide a comparable cost curve, prototype yield or production data set for that assertion.

This is therefore a decision about Micron’s path, not a sector-wide ruling on 4F². TrendForce reported that the company plans to extend 6F² while treating 3D DRAM as a longer-term alternative. The IEEE IRDS material still identifies a transition from 6F² to 4F² as one research path for DRAM scaling. That leaves feasibility, manufacturing economics and production timing unresolved across the industry. CXMT has separately said it aims to advance a 4F² server DDR5 RDIMM, but no public product specification, yield or customer qualification supports a cost comparison.

The useful lens is shifting from cell geometry alone to the entire manufacturing chain: capacitor aspect ratio, stacking and bonding, lithography steps, defect control and good bits per wafer all affect cost. Continued 6F² scaling could let Micron avoid an intermediate architecture transition. Conversely, bypassing 4F² could create a difficult bridge if 3D integration, thermal management or yield does not meet expectations. No public disclosure yet gives comparable timing or unit-cost data for Micron’s 3D DRAM path.

The next evidence to watch is concrete: node, bonding or 3D-DRAM production timing and unit-cost indicators from Micron; disclosed 4F² die area, yield and product specifications from other vendors; and customer qualification that turns these structures into shippable DDR products. Until then, Micron’s statement is best read as a company-level technology-economics choice, not proof that the industry has abandoned 4F².